1. Field
This disclosure relates generally to semiconductors, and more specifically, to circuitry and a process for testing semiconductor device functionality.
2. Related Art
Transistors and other semiconductor devices are often tested for functional operating characteristics by placing such devices on a semiconductor wafer between integrated circuit die. Such transistors are tested prior to singulating the integrated circuit die and are efficient by not using the area within the integrated circuit. However, such known test devices have decided disadvantages. In one known implementation, each test device has one or more wafer probing pads which consume a large amount of area per test device. To reduce the total area required for multiple test devices, test devices have been connected together in parallel. In this parallel configuration the off-state leakage current is significant, thereby preventing the measurement of a single test device's leakage current. Additionally, a parallel test structure fails when only one of the test devices is faulty and causes an electrical short-circuit. Another alternative for implementing test devices is to use CMOS transmission gates to isolate test devices that are connected in parallel. Such transmission gates have lower leakage current when implemented with low-leakage transistors, such as those with thicker gate oxide. However, such low-leakage transmission gates add significant resistance and still have some non-zero leakage current that becomes significant when large numbers of test devices are connected in parallel. Therefore, the leakage current can become greater than the small current values desired to be measured.